This invention relates to a drive circuit for an insulated gate type of transistor, which is operable to increase the noise immunity of the transistor.
There are numerous designs of power circuits wherein a transistor is turned on and off and thereby controls the current flow to a load. For example, one type of DC to AC inverter includes a number of switch blocks or modules, each including an insulated gate transistor which is switched on and off by control signal pulses.
A problem encountered with a circuit of the above character arises from the fact that high voltage noise is frequently present on the DC power bus, due, for example, to switching transients. During power up and when the power transistor is turned off for an extended period of time, there is a danger that a high voltage noise signal on the bus may turn on the power transistor and disrupt the circuit and the components.
Circuits have been provided in the prior art for protecting transistors from noise problems. For example, the D.F. Horan U.S. Pat. No. 4,296,340 shows a noise protection circuit for a MOSFET transistor, wherein depletion mode transistors shunt the gates of MOSFET transistors to ground during circuit power up conditions. The Horan circuit does not, however, provide protection from noise when no control signals appear at the gate of the MOSFET transistor for a given time period.
In addition to the above Horan patent, the circuits shown in the following U.S. patents are also known but are not believed to be more pertinent than the Horan patent:
Y Idaka et al. U.S. Pat. No. 4,801,822 W.J. Janutka U.S. Pat. No. 4,500,801 PA1 P.R.K. Chetty et al U.S. Pat. No. 4,625,271. R.D.W. Shelly U.S. Pat. No. 4,423,341; PA1 C Okado U.S. Pat. No. 4,721,869; A.G.V. Grace U.S. Pat. No. 4,651,271
D.G. Miller U.S. Pat. No. 4,455,526;, T.N. Rao et al. U.S. Pat. No. 4,220,987.
It is a general object of the present invention to provide an improved circuit for providing noise immunity.